The manufacturing costs of integrated circuits are largely dependent upon the chip area required to implement desired functions. The chip area, in turn, is defined by the geometries and sizes of the active components such as gate electrodes in metal-oxide-semiconductor (MOS) technology, and diffused regions such as MOS source and drain regions and bipolar emitters and base regions. These geometries and sizes are often dependent upon the photolithographic resolution available fort he particular manufacturing facility. The goal of photolithography in establishing the horizontal dimensions of the various devices and circuits is to create a pattern which meets design requirements as well as to correctly align the circuit pattern on the surface of the wafer. As line widths shrink smaller and smaller in submicron photolithography, the process to print lines and contact holes in photoresist becomes increasingly more difficult.
With circuit advancement to the very-large-scale integration (VLSI) levels, more and more layers are added to the surface of the wafer. These additional layers in turn create more steps on the wafer surface. The resolution of small image sizes in photolithography thus becomes more difficult over the additional steps due to light reflection and the thinning of the photoresists over the steps. Planarization techniques are generally incorporated to offset the effects of a varied topography.
In addition to the planarization techniques used to increase photolithographic resolution, the chip area also depends on the isolation technology used. Sufficient electrical isolation must be provided between active circuit elements so that leakage current does not cause functional or specification failures. Increasingly stringent specifications, together with the demand, for example, for smaller memory cells in denser memory arrays, places significant pressure on the isolation technology in memory devices, as well as in other modern integrated circuits.
A well-known and widely-used isolation technique is the local oxidation of silicon, commonly referred to as LOCOS. The LOCOS process was a great technological improvement in reducing the area needed for the isolation regions and decreasing some parasitic capacitances. LOCOS field oxide is generally formed to a sufficient thickness that a conductor placed over the field oxide will not invert the channel underneath, when biased to the maximum circuit voltage. The LOCOS field oxide, however, as well as other isolation techniques, adds topography to the integrated circuit surface. The additional topography is a result of the silicon dioxide necessarily occupying a greater volume than that of the silicon prior to its oxidation, due to the reaction of the silicon to oxygen. As a result, the surface of conventional LOCOS field oxide is above the surface of the active regions, with approximately half of the oxide thickness being above the active region surface. This topography requires overlying conductors to cover steps at the edges of the field oxide which presents the potential for problems in etching the conductor layer and in the reliability of the conductor layer. In addition, the depth of field for submicron photolithography can be exceeded by the topography of the wafer surface.
It is therefore an object of this invention to provide a method of forming an isolation structure having a surface which is substantially coplanar with the surface of the adjacent active regions.
It is a further object of this invention to provide such a method which can be used for both wide and narrow isolation locations.
It is a further object of this invention to provide such a method which utilizes thermal silicon dioxide as the isolation material.
It is a further object of this invention to provide such a method which substantially fills the isolation recesses with a planarizing insulating layer.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.